The subject matter disclosed herein relates to solutions for inducing stress in a Complementary Metal Oxide Semiconductor (CMOS). More specifically, the subject matter disclosed herein relates to systems and methods for forming a nitride stress liner in a CMOS device.
Semiconductor device designers continually work to make semiconductor devices smaller while increasing their level of performance. One approach to increasing performance is the use of stress liners over portions of these devices. Stress liners may be particularly helpful, for example, in increasing electron/hole mobility in device channels. However, stress liners located near device channels may cause complications during contact formation, and may adversely affect device performance.